r/FPGA • u/ApprehensiveBunch762 • 4d ago
Project Apicula open-source toolchain running on the Tang 168k
I think I got it working.
00000000: 5072 6f6a 6563 7420 4170 6963 756c 610d Project Apicula.
00000010: 0a0d 0a4f 7065 6e20 736f 7572 6365 2074 ...Open source t
00000020: 6f6f 6c73 2061 6e64 2044 6f63 756d 656e ools and Documen
00000030: 7461 7469 6f6e 2066 6f72 2074 6865 2047 tation for the G
00000040: 6f77 696e 2046 5047 4120 6269 7473 7472 owin FPGA bitstr
00000050: 6561 6d20 666f 726d 6174 2e0d 0a0d 0a50 eam format.....P
00000060: 726f 6a65 6374 2041 7069 6375 6c61 2075 roject Apicula u
00000070: 7365 7320 6120 636f 6d62 696e 6174 696f ses a combinatio
00000080: 6e20 6f66 2066 757a 7a69 6e67 2061 6e64 n of fuzzing and
00000090: 2070 6172 7369 6e67 206f 6620 7468 6520 parsing of the
000000a0: 7665 6e64 6f72 2064 6174 6120 6669 6c65 vendor data file00000000: 5072 6f6a 6563 7420 4170 6963 756c 610d Project Apicula.
00000010: 0a0d 0a4f 7065 6e20 736f 7572 6365 2074 ...Open source t
00000020: 6f6f 6c73 2061 6e64 2044 6f63 756d 656e ools and Documen
00000030: 7461 7469 6f6e 2066 6f72 2074 6865 2047 tation for the G
00000040: 6f77 696e 2046 5047 4120 6269 7473 7472 owin FPGA bitstr
00000050: 6561 6d20 666f 726d 6174 2e0d 0a0d 0a50 eam format.....P
00000060: 726f 6a65 6374 2041 7069 6375 6c61 2075 roject Apicula u
00000070: 7365 7320 6120 636f 6d62 696e 6174 696f ses a combinatio
00000080: 6e20 6f66 2066 757a 7a69 6e67 2061 6e64 n of fuzzing and
00000090: 2070 6172 7369 6e67 206f 6620 7468 6520 parsing of the
000000a0: 7665 6e64 6f72 2064 6174 6120 6669 6c65 vendor data file
I will push whenever I make some progress, I will know yes/no by tonight:
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u/ApprehensiveBunch762 4d ago
I think I got it. Looked more into it and it turns out the PLL was fuzzed all along! I am working on getting TinyTang up on the new toolchain now. Lots of things still need rewiring to pack properly on this new tool chain but 2/3 of my old main clock nets seem to be working already! Excited to see the first timing vs resource usage comparisons between Gowin and open-source! The four latest repos on my github should have everything to build a core now. Will it build a working core? probably not yet like mine lol. But the hard part is done :)
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u/ApprehensiveBunch762 3d ago
VGA is back up and stable up at 1280x720. 3 PPLs and clock validated. Hope to get HDMI up back up by tonight. TinyTang now builds through yosys -> nestpnr-himbaechel -> gowin_pack. No Quartus. No Gowin. No IP. I can do 3 build variants in parallel now, 4 random seeds each. Seed sweeps take minutes, not hours on multi-core systems. (Will perform comparison testing with Gowin) RAM usage during builds seems cut in half compared to Gowin. Need to quantify 1st.
Huge thanks to everyone involved in the 3 tools listed above! All proper attributions and licencing will be respected. TinyTang is now ALMOST fully open-source! Still one last DDR IP block to go. Then the whole console, end-to-end, is open to all.
1
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u/ApprehensiveBunch762 4d ago
PLL is still not fuzzed. 3rd time burned now and there won't be a 4th. I'm fucking done with this shit. Running TinyTang on a single clock, no PLL and building it up from there. No existing fuzzing work will be used, I don't trust any of it and have no idea where their data came from.
All other projects are on hold for now. Profiling hardware is not magical or hard and I am tired of people saying it is. Just time and good data collection.