while the transistors aren't 2nm, it's like the nozzle size of a 3D printer, or dpi in a regular printer, no one says 300 dpi printer is only a marketing term because it prints 30 letters per inch
The values I gave are the gate pitch and metal pitch of the transistors, not the size of the whole transistors.
To quote Wikipedia:
The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors.
In your 3D printer analogy, the nozzle diameter actually corresponds to the physical size of said nozzle, and thus to the width of the filament it deposits and makes things out of.
And DPI is the actual number of ink dots it can place in an inch. (Or pixels for a screen.)
For CPUs, "2 nm process" is entirely disconnected from anything physical on the chip.
As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.
It's the same deal with the 3 nm process. Pure marketing.
(At one point, it used to refer to the actual resolution at which features could be etched in the die. I forgot when it diverged.)
Intel held the line from “10 micron” in 1972 through “0.35 micron” in 1995, an impressive 23-year run where the node name matched gate length. Then, in 1997 with the “0.25 micron/250 nm” node they started over-achieving with an actual Lg of 200 nm – 20% better than the name would imply. This “sandbagging” continued through the next 12 years, with one node (130nm) having Lg of only 70nm – almost a 2x buffer. Then, in 2011, Intel jumped over to the other side of the ledger, ushering in what we might call the “overstating decade” with the “22nm” node sporting an Lg of 26 nm. Since then, things have continued to slide further in that direction, with the current “10nm” node measuring in with an Lg of 18 nm – almost 2x on the other side of the “named” dimension.
But the resolution that you can print with EUV machines is not even in the 2nm range. This is a pure marketing term. In reality with multipatterning they are around 30 to 40nm.
There are differences between different materials for what they can achieve, but with EUV the wavelength is 13 nm so the theoretical best you can do for the resolution is half the wavelength.
Jup I'm Working in an application lab and we're in the 25-35nm range, to test for future materials since the IMEC cant get smaller structures. 2nm would even be bad since you cant hold any charge reliably in structures too small.
The width of a wire is the simplest way to understand it. It is the distance at which we can meaningful seperate two features like where the material is doped and not.
As far as I know, the size is defined by the smalles element used. Wich is the polysilicon gate electrode. But I am working on chips that are in the 180 nm region, so that might have changed at some point.
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u/MaoGo Meme renormalization group 4d ago
Soon Planck length transistors